1. Field of the Invention
The present invention relates to communication transceiver clock and data recovery, and, in particular, to detecting and correcting for cycle slip of data sampling.
2. Description of the Related Art
In many data communication applications, Serializer and De-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss from the communications channel (e.g., the signal path between the two end points of a serial link) as well as signal dispersion and distortion can occur. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal. Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality. Equalization may also be employed at the transmit side to pre-condition the signal. Equalization, a form of filtering, generally requires some estimate of the transfer function of the channel to set its filter parameters. However, in many cases, the specific frequency-dependent signal degradation characteristics of a communications channel are unknown, and often vary with time. In such cases, an equalizer with adaptive setting of parameters providing sufficient adjustable range might be employed to mitigate the signal degradation of the signal transmitted through the communications channel. An automatic adaptation process is often employed to adjust the equalizer's response. Equalization might be through a front end equalizer, a feedback equalizer, or some combination of both.
FIG. 1 shows a data eye diagram 100 overlaid with exemplary data sampler (DS) 102. Data eye diagram 100 illustrates super-positions of many data eyes of signal transitions expressed in amplitude versus time (in unit interval, or “UI”, corresponding to a symbol period). The data eye is created as signals transition from low to low, low to high, high to low and high to high. The data sampler, along with top, center and/or bottom transition samplers (illustrated as a single, center transition sampler (TS) 103 in FIG. 1) are placed in the data stream to capture the frequency and phase of the data transitions, and this timing is then used by a clock and data recovery circuit to set correct frequency and phase of a sampling clock. Further, error samplers, shown in FIG. 1 as top and bottom error samplers ES 104 and 105, respectively, are placed in the data eye to generate error samples to detect timing and/or amplitude error for use by adaptation and tracking algorithms. As employed herein, “placing” a sampler (latch) in a data stream requires setting a voltage threshold and clocking phase of the sampler to detect a predetermined point in the data eye. Clocking the data sampler with a clock signal with known frequency and phase derived with respect to the detected symbol transitions of data allows for clock recovery of symbols within the data stream generating the eye. Thus, “placing” a data sampler in the signal path with a threshold and sampling clock equivalent to the amplitude and timing at the center of the eye corresponds to correct sampling to make a decision as to the value of a received data symbol.
Ideally, without noise, jitter, and other loss and dispersion effects, the data eye will exhibit a relatively ideal shape, illustrated as ideal eye 110. In practice, as described previously, the shape of the data eye changes, illustrated as actual eye 111, with noise, jitter, ISI, other loss and dispersion effects, and temperature and voltage variations. The shape of the data eye also changes due to equalization applied to input signal of the receiver. In some systems, equalization is also applied by a transmitter's equalizer, further altering the shape of the eye from the ideal. After equalization, the inner eye of the transceiver is open, with some margin for supporting channels. If a simple, analog front-end equalizer (AFE) is employed, the data eye operating margin improves. However, better performance might be achieved through use of a Decision Feedback Equalizer (DFE) in combination with an AFE. Classical DFE equalization optimizes for ISI and opens up the vertical and horizontal data eye opening.
Initially, however, the high speed SerDes receiver brings up the receiver by first achieving clock recovery with a clock and data recovery circuit (CDR) in presence of a relatively closed data eye. Later, data recovery integrity is achieved through proper equalization with respect to a specified bit error rate (BER) target threshold. The data recovery integrity is achieved through a process of gain adaptation as well as transmitter tap equalization along with receiver equalization. Receiver equalization is further divided into two separate equalization adaptation operations, such as for the analog equalizer equalization and the decision feedback equalization. While these equalization processes are taking place, the signal integrity might be severely degraded due to direct signal distortion as well as sampling skew variation. This dynamic behavior might cause the CDR to diverge, causing errors in the adaptation process and possibly a system start-up failure. Typically, occasional divergence requires start-up recovery that is performed by a link layer of the receiver by i) operating the SerDes receiver at a reduced speed or ii) multiple retries, both of which techniques might cause system boot-up delays.